Robust and Efficient Hardware-based Evolutionary Technique for Multi-objective Optimisation in Aerospace
The motivation for this thesis stems from the interest to address the computational time complexity of evolutionary computation techniques. Investigations into parallel computing concepts through digital hardware-based designs are carried out for improving computation run-time and meeting constraints of highly automated aircraft systems.
Evolutionary algorithm (EA) is an effective evolutionary computation technique that is widely used in many fields of research and development. Fundamentally, EA is a generic population-based metaheuristic optimisation algorithm that employs features inspired by biological evolution. The practical applications of EAs are limited by the heavy computational overhead that arises from the complexity of real-world scenarios, especially when applied to aerospace optimisation problems. EAs are therefore rarely used as an on-board optimisation method for unmanned aerial vehicles (UAVs) or highly automated aircraft systems where flight computer processor power is limited. A few of the common ways to address this issue is to simplify the optimisation problem, run an EA offline or use a compromised algorithm in place of an EA.
The key to realising the full potential of EAs lies in addressing the algorithm design from a lower level. Although EAs were originally designed and intended to run sequentially, they opportunistically have inherent parallelism potentials that are attributed to their population-based characteristics and the low dependency of individuals in the population. One method for exploiting parallelism of an algorithm is by re-designing it for a hardware circuit implementation. Field programmable gate array (FPGA) is an integrated circuit device that is reprogrammable and allows for concurrent data processing. FPGA technology offers efficient extraction of parallelism through the flexibility of reconfigurable logic resources. Additionally, being compact in size, light in weight, and low in power consumption, FPGAs are ideal computing platforms for UAVs and highly automated aircraft systems where flight computers and processors have to adhere to strict size, weight, and power constraints.
The primary aim of this thesis is to provide knowledge that contributes to the design methodologies and architectures needed to directly map EAs on an FPGA hardware device. Furthermore, the knowledge discovered offers a greater degree of confidence concerning the effectiveness of developing and implementing FPGA-based EAs. One of the key challenges in designing an efficient FPGA-based architecture is the need to directly map the EA onto a hardware design without compromising the original algorithmic integrity, which is not straightforward. The outcomes of this research have produced design methodologies and architectures of hardware-based EAs for solving aerospace optimisation problems on FPGAs. This research investigation encompasses both FPGA-based single-objective and multi-objective EAs. The robustness and effectiveness of FPGA-based EAs have been demonstrated via evaluation across several practical aerospace optimisation applications, which exhibits different problem characteristics, such as path planning, travelling salesman problem, and multi-objective test function. Overall, the proposed FPGA-based EAs offer advantages including meeting physical constraints in aerospace applications and performance speedups without compromising the integrity of the evolutionary technique. This research is a step forward towards the advancement of efficient UAVs and highly automated aircraft systems.